This paper details the study of systolic architectures for fuzzy rules processing made at the Hardware and Advanced Control Laboratory - INTA. The theoretical basis of these architectures is described and analysed. Likewise, the resultant schematics are simulated using a hardware description language (VHDL) with standard cells from ES2. This gives us a very accurate assessment of their real performance. In this way we can detect the inherent shortcomings in this class of systems and we outline several ways of overcoming them.
@article{urn:eudml:doc:39034,
title = {Systolic architectures for fuzzy processing and their simulation.},
journal = {Mathware and Soft Computing},
volume = {1},
year = {1994},
pages = {297-308},
language = {en},
url = {http://dml.mathdoc.fr/item/urn:eudml:doc:39034}
}
Salvador, Luis de; García, Marcos; Gutiérrez, Julio. Systolic architectures for fuzzy processing and their simulation.. Mathware and Soft Computing, Tome 1 (1994) pp. 297-308. http://gdmltest.u-ga.fr/item/urn:eudml:doc:39034/