Dependability Evaluation of Time Triggered Architecture Using Simulation
Stanislav Racek ; Pavel Herout ; Jan Hlavička
Computing and Informatics, Tome 28 (2012) no. 1, / Harvested from Computing and Informatics
The method presented in this paper uses a generic C-language written simulation model of an embedded distributed computer system aimed for a safety-critical control application. The considered system is built using Time Triggered Architecture (TTA) concepts. The aim of the presented simulation method is to evaluate the system capability to tolerate a chosen category of faults. The model, being written in ANSI-C, is portable and machine-independent. Its structure is modular and flexible, so that the system to be studied and the experiment setting can easily be changed. The functionality of this model is demonstrated on a set of fault injection experiments aimed mainly to evaluate the correctness of the Time Triggered Protocol (TTP/C) that implements the abstract concepts of TTA. These experiments were done within the EU/IST project Fault Injection for Time triggered architecture (FIT).
Publié le : 2012-01-26
Classification:  Dependability; simulation; TTA; fault-injection; C-Sim
@article{cai408,
     author = {Stanislav Racek and Pavel Herout and Jan Hlavi\v cka},
     title = {Dependability Evaluation of Time Triggered Architecture Using Simulation},
     journal = {Computing and Informatics},
     volume = {28},
     number = {1},
     year = {2012},
     language = {en},
     url = {http://dml.mathdoc.fr/item/cai408}
}
Stanislav Racek; Pavel Herout; Jan Hlavička. Dependability Evaluation of Time Triggered Architecture Using Simulation. Computing and Informatics, Tome 28 (2012) no. 1, . http://gdmltest.u-ga.fr/item/cai408/