Pipeline Implementation of Peer Group Filtering in FPGA
Tomasz Kryjak; AGH University of Science and Technology, al. Mickiewicza 30, 30-065 Cracow ; Marek Gorgon; AGH University of Science and Technology, al. Mickiewicza 30, 30-065 Cracow
Computing and Informatics, Tome 28 (2012) no. 1, / Harvested from Computing and Informatics
Text on Computing and Informatics
In the paper a parallel FPGA implementation of the Peer Group Filtering algorithm is described. Implementation details, results, performance of the design and FPGA logic resources are discussed. The PGF algorithm customized for FPGA is compared with the original one and Vector Median Filtering.
Publié le : 2012-10-03
Classification:  Colour image processing, reconfigurable systems, FPGA, parallel algorithms 
@article{cai1102,
     author = {Tomasz Kryjak; AGH University of Science and Technology, al. Mickiewicza 30, 30-065 Cracow and Marek Gorgon; AGH University of Science and Technology, al. Mickiewicza 30, 30-065 Cracow},
     title = {Pipeline Implementation of Peer Group Filtering in FPGA},
     journal = {Computing and Informatics},
     volume = {28},
     number = {1},
     year = {2012},
     language = {en},
     url = {http://dml.mathdoc.fr/item/cai1102}
}

Tomasz Kryjak; AGH University of Science and Technology, al. Mickiewicza 30, 30-065 Cracow; Marek Gorgon; AGH University of Science and Technology, al. Mickiewicza 30, 30-065 Cracow. Pipeline Implementation of Peer Group Filtering in FPGA. Computing and Informatics, Tome 28 (2012) no. 1, . http://gdmltest.u-ga.fr/item/cai1102/