Stability of the 4-2 Binary Addition Circuit Cells. Part I
Katsumi Wasaki
Formalized Mathematics, Tome 16 (2008), p. 377-387 / Harvested from The Polish Digital Mathematics Library
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To evaluate our formal verification method on a real-size calculation circuit, in this article, we continue to formalize the concept of the 4-2 Binary Addition Cell primitives (FTAs) to define the structures of calculation units for a very fast multiplication algorithm for VLSI implementation [11]. We define the circuit structure of four-types FTAs, TYPE-0 to TYPE-3, using the series constructions of the Generalized Full Adder Circuits (GFAs) that generalized adder to have for each positive and negative weights to inputs and outputs [15]. We then successfully prove its circuit stability of the calculation outputs after four-steps. The motivation for this research is to establish a technique based on formalized mathematics and its applications for calculation circuits with high reliability.MML identifier: FTACELL1, version: 7.9.03 4.108.1028

Publié le : 2008-01-01
EUDML-ID : urn:eudml:doc:266881 
@article{bwmeta1.element.doi-10_2478_v10037-008-0046-7,
     author = {Katsumi Wasaki},
     title = {Stability of the 4-2 Binary Addition Circuit Cells. Part I},
     journal = {Formalized Mathematics},
     volume = {16},
     year = {2008},
     pages = {377-387},
     language = {en},
     url = {http://dml.mathdoc.fr/item/bwmeta1.element.doi-10_2478_v10037-008-0046-7}
}

Katsumi Wasaki. Stability of the 4-2 Binary Addition Circuit Cells. Part I. Formalized Mathematics, Tome 16 (2008) pp. 377-387. http://gdmltest.u-ga.fr/item/bwmeta1.element.doi-10_2478_v10037-008-0046-7/

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