Optimization methods of logic circuits for Moore finite-state machines are proposed. These methods are based on the existence of pseudoequivalent states of a Moore finite-state machine, a wide fan-in of PAL macrocells and free resources of embedded memory blocks. The methods are oriented to hypothetical VLSI microcircuits based on the CPLD technology and containing PAL macrocells and embedded memory blocks. The conditions of effective application of each proposed method are shown. An algorithm to choose the best model of a finite-state machine for given conditions is proposed. Examples of proposed methods application are given. The effectiveness of the proposed methods is also investigated.
@article{bwmeta1.element.bwnjournal-article-amcv17i4p565bwm,
author = {Barkalov, Alexander and Titarenko, Larysa and Chmielewski, S\l awomir},
title = {Reduction in the number of PAL macrocells in the circuit of a Moore FSM},
journal = {International Journal of Applied Mathematics and Computer Science},
volume = {17},
year = {2007},
pages = {565-575},
language = {en},
url = {http://dml.mathdoc.fr/item/bwmeta1.element.bwnjournal-article-amcv17i4p565bwm}
}
Barkalov, Alexander; Titarenko, Larysa; Chmielewski, Sławomir. Reduction in the number of PAL macrocells in the circuit of a Moore FSM. International Journal of Applied Mathematics and Computer Science, Tome 17 (2007) pp. 565-575. http://gdmltest.u-ga.fr/item/bwmeta1.element.bwnjournal-article-amcv17i4p565bwm/
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