Evaluating the Kernighan-Lin heuristic for hardware/software partitioning
Mann, Zoltán ; Orbán, András ; Farkas, Viktor
International Journal of Applied Mathematics and Computer Science, Tome 17 (2007), p. 249-267 / Harvested from The Polish Digital Mathematics Library

In recent years, several heuristics have been proposed for the hardware/software partitioning problem. One of the most promising directions is the adaptation of the Kernighan-Lin algorithm. The Kernighan-Lin heuristic was originally developed for circuit partitioning, but it has been adapted to other domains as well. Moreover, numerous improvements have been suggested so that now several variants of the original algorithm exist. The aim of this paper is to systematically evaluate the possibilities of applying the Kernighan-Lin heuristic to hardware/software partitioning. It is investigated in detail which versions of the heuristic work well in this context. Since hardware/software partitioning also has several formulations, it is also discussed how the problem formulation affects the applicability of this heuristic. Furthermore, possibilities of efficient implementations of the algorithm - by using appropriate data structures - are also presented. These investigations are accompanied by numerous empirical test results.

Publié le : 2007-01-01
EUDML-ID : urn:eudml:doc:207835
@article{bwmeta1.element.bwnjournal-article-amcv17i2p249bwm,
     author = {Mann, Zolt\'an and Orb\'an, Andr\'as and Farkas, Viktor},
     title = {Evaluating the Kernighan-Lin heuristic for hardware/software partitioning},
     journal = {International Journal of Applied Mathematics and Computer Science},
     volume = {17},
     year = {2007},
     pages = {249-267},
     zbl = {1126.68002},
     language = {en},
     url = {http://dml.mathdoc.fr/item/bwmeta1.element.bwnjournal-article-amcv17i2p249bwm}
}
Mann, Zoltán; Orbán, András; Farkas, Viktor. Evaluating the Kernighan-Lin heuristic for hardware/software partitioning. International Journal of Applied Mathematics and Computer Science, Tome 17 (2007) pp. 249-267. http://gdmltest.u-ga.fr/item/bwmeta1.element.bwnjournal-article-amcv17i2p249bwm/

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