Fast Hardware Implementations of Static P Systems

Juan Quiros; ID2 Group, Department of Electronic Technology, University of Seville, 41012, Sevilla; Sergey Verlan; LACL, Departement Informatique, Universite Paris Est, 94010 Creteil; Julian Viejo; ID2 Group, Department of Electronic Technology, University of Seville, 41012, Sevilla; Alejandro Millan; ID2 Group, Department of Electronic Technology, University of Seville, 41012, Sevilla; Manuel J. Bellido; ID2 Group, Department of Electronic Technology, University of Seville, 41012, Sevilla

Juan Quiros; ID2 Group, Department of Electronic Technology, University of Seville, 41012, Sevilla ; Sergey Verlan; LACL, Departement Informatique, Universite Paris Est, 94010 Creteil ; Julian Viejo; ID2 Group, Department of Electronic Technology, University of Seville, 41012, Sevilla ; Alejandro Millan; ID2 Group, Department of Electronic Technology, University of Seville, 41012, Sevilla ; Manuel J. Bellido; ID2 Group, Department of Electronic Technology, University of Seville, 41012, Sevilla

Computing and Informatics, Tome 34 (2016) no. 4, / Harvested from Computing and Informatics

Text on Computing and Informatics

Résumé

In this article we present a simulator of non-deterministic static P systems using Field Programmable Gate Array (FPGA) technology. Its major feature is a high performance, achieving a constant processing time for each transition. Our approach is based on representing all possible applications as words of some regular context-free language. Then, using formal power series it is possible to obtain the number of possibilities and select one of them following a uniform distribution, in a fair and non-deterministic way. According to these ideas, we yield an implementation whose results show an important speed-up, with a strong independence from the size of the P system.

Publié le : 2016-11-02
Classification: Computer Architectures and Networking ; Parallel and Distributed Computing, Reconfigurable hardware, P systems, static P systems, FPGA, membrane computing, parallel implementations of membrane computing, simulator of membrane computing, hardware implementations of membrane computing, parallel implementations of static P systems, 94-04 ; 68-04 ; 68U20

@article{cai1665,
     author = {Juan Quiros; ID2 Group, Department of Electronic Technology, University of Seville, 41012, Sevilla and Sergey Verlan; LACL, Departement Informatique, Universite Paris Est, 94010 Creteil and Julian Viejo; ID2 Group, Department of Electronic Technology, University of Seville, 41012, Sevilla and Alejandro Millan; ID2 Group, Department of Electronic Technology, University of Seville, 41012, Sevilla and Manuel J. Bellido; ID2 Group, Department of Electronic Technology, University of Seville, 41012, Sevilla},
     title = {Fast Hardware Implementations of Static P Systems},
     journal = {Computing and Informatics},
     volume = {34},
     number = {4},
     year = {2016},
     language = {en},
     url = {http://dml.mathdoc.fr/item/cai1665}
}

Juan Quiros; ID2 Group, Department of Electronic Technology, University of Seville, 41012, Sevilla; Sergey Verlan; LACL, Departement Informatique, Universite Paris Est, 94010 Creteil; Julian Viejo; ID2 Group, Department of Electronic Technology, University of Seville, 41012, Sevilla; Alejandro Millan; ID2 Group, Department of Electronic Technology, University of Seville, 41012, Sevilla; Manuel J. Bellido; ID2 Group, Department of Electronic Technology, University of Seville, 41012, Sevilla. Fast Hardware Implementations of Static P Systems. Computing and Informatics, Tome 34 (2016) no. 4, . http://gdmltest.u-ga.fr/item/cai1665/