Energy consumption in a Chip MultiProcessor (CMP) is one of the most important costs. It is related to design aspects such as thermal and power constrains. Besides efficient on-chip processing elements, a well-designed Processor Allocator (PA) and a Network-on-Chip (NoC) are also important factors in the energy budget of novel CMPs. In this paper, the authors propose an energy model for NoCs with 2D-mesh and 2D-torus topologies. All important NoC architectures are described and discussed. Energy estimation is presented for PAs. The estimation is based on synthesis results for PAs targeting FPGA. The PAs are driven by allocation algorithms that are studied as well. The proposed energy model is employed in a simulation environment, where exhaustive experiments are performed. Simulation results show that a PA with an IFF allocation algorithm for mesh systems and a torus-based NoC with express-virtual-channel flow control are very energy efficient. Combination of these two solutions is a clear choice for modern CMPs.
@article{bwmeta1.element.bwnjournal-article-amcv21i2p385bwm,
author = {Dawid Zydek and Henry Selvaraj and Grzegorz Borowik and Tadeusz \L uba},
title = {Energy characteristic of a processor allocator and a network-on-chip},
journal = {International Journal of Applied Mathematics and Computer Science},
volume = {21},
year = {2011},
pages = {385-399},
language = {en},
url = {http://dml.mathdoc.fr/item/bwmeta1.element.bwnjournal-article-amcv21i2p385bwm}
}
Dawid Zydek; Henry Selvaraj; Grzegorz Borowik; Tadeusz Łuba. Energy characteristic of a processor allocator and a network-on-chip. International Journal of Applied Mathematics and Computer Science, Tome 21 (2011) pp. 385-399. http://gdmltest.u-ga.fr/item/bwmeta1.element.bwnjournal-article-amcv21i2p385bwm/
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