Two methods are proposed targeted at reduction in the number of look-up table elements in logic circuits of compositional microprogram control units (CMCUs) with code sharing. The methods assume the application of field-programmable gate arrays for the implementation of the combinational part of the CMCU, whereas embedded-memory blocks are used for implementation of its control memory. Both methods are based on the existence of classes of pseudoequivalent operational linear chains in a microprogram to be implemented. Conditions for the application of the proposed methods and examples of design are shown. Results of conducted experiments are given.
@article{bwmeta1.element.bwnjournal-article-amcv20i4p751bwm,
author = {Alexander Barkalov and Larysa Titarenko and Jacek Bieganowski},
title = {Reduction in the number of LUT elements for control units with code sharing},
journal = {International Journal of Applied Mathematics and Computer Science},
volume = {20},
year = {2010},
pages = {751-761},
language = {en},
url = {http://dml.mathdoc.fr/item/bwmeta1.element.bwnjournal-article-amcv20i4p751bwm}
}
Alexander Barkalov; Larysa Titarenko; Jacek Bieganowski. Reduction in the number of LUT elements for control units with code sharing. International Journal of Applied Mathematics and Computer Science, Tome 20 (2010) pp. 751-761. http://gdmltest.u-ga.fr/item/bwmeta1.element.bwnjournal-article-amcv20i4p751bwm/
[000] Adamski, M. and Barkalov, A. (2006). Architectural and Sequential Synthesis of Digital Devices, University of Zielona Góra Press, Zielona Góra.
[001] Altera (2010). Altera corpotation webpage, http://www.altera.com
[002] Baranov, S. (2008). Logic and System Design of Digital Systems, TUT Press, Tallinn.
[003] Barkalov, A. and Titarenko, L. (2008). Logic Synthesis for Compositonal Microprogram Control Units, Springer, Berlin. | Zbl 1156.93003
[004] Barkalov, A., Titarenko, L. and Wiśniewski, R. (2006). Synthesis of compositional microprogram control units with sharing codes and address decoder, Proceedings of the International Conference on Mixed Design of Integrated Circuits and Systems, MIXDES 2006, Gdynia, Poland, pp. 397-400.
[005] Borowik, G., Falkowski, B. and Łuba, T. (2007). Cost-efficient synthesis for sequetnial circuits implemented using embedded memory blocks of FPGA's, Proceedings of the IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Cracow, Poland, pp. 99-104.
[006] Czerwiński, R. and Kania, D. (2004). State assignment method for high speed FSM, Proceedings of the IFAC Workshop on Programmable Devices and Systems, PDS, Cracow, Poland, pp. 216-221.
[007] Eastlake, D. and Jones, P. (2001). RFC:3174 US secure hash algorithm 1 (SHA1), Technical report, Network Working Group, http://www.faqs.org/rfcs/rfc3174.html.
[008] Escherman, B. (1993). State assignment for hardwired VLSI control units, ACM Computing Surveys 25(4): 415-436.
[009] Jarvinen, K., Tommiska, M. and Skytta, J. (2005). Hardware implementation analysis of the MD5 hash algorithm, HICSS'05: Proceedings of the 38th Annual Hawaii Interenational Conference on System Sciences, Waikoloa, Hi, USA, p. 298.1.
[010] Kam, T., Villa, T., Brayton, R. and Sangiovanni-Vincentelli, A. (1998). A Synthesis of Finie State Machines: Functional Optimization, Kluwer Academic Publishers, Boston, MA. | Zbl 0876.94056
[011] Kania, D. (2004). Logic Synthesis for PAL-Based Complex Programmable Logic Devices, Scientific Fascicles of the Silesian University of Technology, Gliwice, (in Polish).
[012] Kołopieńczyk, M. (2008). Application of Address Converter for Decreasing Memory Size of Compositional Microprogram Control Unit with Code Sharing, University of Zielona Góra Press, Zielona Góra.
[013] Maxfield, C. (2004). The Design Warrior's Guide to FPGAs, Academic Press, Orlando, FL.
[014] Micheli, G.D. (1994). Synthesis and Optimization of Digital Circuits, McGraw-Hill, New York, NY.
[015] Navabi, Z. (2007). Embedded Core Design with FPGAs, McGraw-Hill, New York, NY.
[016] Rivest, R. (1992). RFC:1312 the MD5 message-digest algorithm, Technical report, Network Working Group, http://www.faqs.org/rfcs/rfc1312.html.
[017] Scholl, C. (2001). Functional Decomosition with Application of FPGA Synthesis, Kluwer Academic Publishers, Boston, MA. | Zbl 0989.94003
[018] Sentovich, E., Singh, K., Lavagno, L., Moon, C., Murgai, R., Saldanha, A., Savoj, H., Stephan, P., Brayton, R.K. and Sangiovanni-Vincentelli, A.L. (1992). SIS: A system for sequential circuit synthesis, Technical Report UCB/ERL M92/41, EECS Department, University of California, Berkeley, CA.
[019] Solovjev, V.V. and Klimowicz, A. (2008). Logic Design for Digital Systems on the Base of Programmable Logic Integerated Circuits, Hot Line-Telecom, Moscow, (in Russian).
[020] Titarenko, L. and Bieganowski, J. (2009). Optimization of compositional microprogram control unit by modification of microinstruction format, Electronics and Telecommunication Quarterly 55(2): 201-214.
[021] Xilinx (2006). Xilinx Synthesis and Simulation Design Guide, Xilinx, http://www.xilinx.com/itp/xilinx9/books/docs/sim/sim.pdf.
[022] Xilinx (2010). Xilinx corpotation webpage, http://www.xilinx.com.
[023] Yang, S. (1991). Logic synthesis and optimization benchmarks user guide, Technical report, Microelectronic Center of North Carolina, Research Triangle Park, NC 27709-2889.