Analysis of multibackground memory testing techniques

Ireneusz Mrozek

International Journal of Applied Mathematics and Computer Science, Tome 20 (2010), p. 191-205 / Harvested from The Polish Digital Mathematics Library

Résumé

March tests are widely used in the process of RAM testing. This family of tests is very efficient in the case of simple faults such as stuck-at or transition faults. In the case of a complex fault model-such as pattern sensitive faults-their efficiency is not sufficient. Therefore we have to use other techniques to increase fault coverage for complex faults. Multibackground memory testing is one of such techniques. In this case a selected March test is run many times. Each time it is run with new initial conditions. One of the conditions which we can change is the initial memory background. In this paper we compare the efficiency of multibackground tests based on four different algorithms of background generation.

Détail

Publié le : 2010-01-01

Zbl 1300.68014

EUDML-ID : urn:eudml:doc:207973

Bibliographie

[000] Cheng, K.-L., Tsai, M.-F. and Wu, C.-W. (2002). Neighborhood pattern sensitive fault testing and diagnostics for random access memories, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 21(11): 1328-1336.

[001] Cockburn, B. F. (1995). Deterministic tests for detecting scrambled pattern-sensitive faults in RAMs, MTDT '95: Proceedings of the 1995 IEEE International Workshop on Memory Technology, Design and Testing, Washington, DC, USA, pp. 117-122.

[002] Franklin, M. and Saluja, K. K. (1996). Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults, IEEE Transactions on CAD of Integrated Circuits and Systems 15(9): 1081-1087.

[003] Goor, A. J. v. d. (1991). Testing Semiconductor Memories: Theory and Practice, John Wiley & Sons, Chichester.

[004] Hayes, J. P. (1975). Detection of pattern-sensitive faults in random-access memories, IEEE Transactions on Computers 24(2): 150-157. | Zbl 0298.94035

[005] Hayes, J. P. (1980). Testing memories for single-cell pattern-sensitive faults, IEEE Transactions on Computers 29(3): 249-254. | Zbl 0431.94054

[006] Huang, Y. and Li, J. F. (2006). Testing active neighborhood pattern-sensitive faults of ternary content addressable memories, European Test Symposium, Southampton, UK, pp. 55-62.

[007] Karpovsky, M. G., Goor, A. J. v. d. and Yarmolik, V. N. (1995). Pseudo-exhaustive word-oriented DRAM testing, EDTC '95: Proceedings of the 1995 European Conference on Design and Test, Washington, DC, USA, p. 126.

[008] Karpovsky, M. G. and Yarmolik, V. N. (1994). Transparent memory testing for pattern-sensitive faults, Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years, Washington, DC, USA, pp. 860-869.

[009] Krasniewski, A. (2008). Concurrent error detection for combinational logic blocks implemented with embedded memory blocks of FPGAs, DDECS'08: Proceedings of the IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems, Bratislava, Slovakia, pp. 74-79.

[010] Mrozek, I. and Yarmolik, V. N. (2008b). Optimal backgrounds selection for multi run memory testing, DDECS'08: Proceedings of the IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems, Bratislava, Slovakia, pp. 332-338.

[011] Mrozek, I. and Yarmolik, V. N. (2008a). MATS+ transparent memory test for pattern sensitive fault detection, MIXDES'08: Proceedings of the 15th International Conference on Mixed Design of Integrated Circuits and Systems, Poznań, Poland, pp. 493-498.

[012] Mrozek, I., Yarmolik, V. N. and Buslowska, E. (2008). Multiple run memory testing for PSF detection, EWDTS '08: Proceedings of the IEEE East-West Design and Test Symposium, Lviv, Ukraine, pp. 125-130.

[013] Nicolaidis, M. (1996). Theory of transparent BIST for RAMs, IEEE Transactions on Computing 45(10): 1141-1156. | Zbl 1057.68613

[014] Niggemeyer, D., Redeker, M. and Otterstedt, J. (1998). Integration of non-classical faults in standard march tests, MTDT '98: Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing, San Jose, CA, USA, p. 91.

[015] Sokol, B. and Yarmolik, S. V. (2006). Address sequences for march tests to detect pattern sensitive faults, DELTA '06: Proceedings of the Third IEEE International Workshop on Electronic Design, Test and Applications, Kuala Lumpur, Malaysia, pp. 354-360.

[016] Sosnowski, J. (2007). Improving software based self-testing for cache memories, Proceedings of the 2nd International Design and Test Workshop, 2007, Cairo, Egypt, pp. 49-54.

[017] Tubbs, J. D. (1989). A note on binary template matching, Pattern Recognition 22(4): 359-366.

[018] Voyiatzis, I. (2006). Accumulator-based compression in symmetric transparent RAM BIST, DTIS'06: Proceedings of the International Conference on Design and Test of Integrated Systems in Nanoscale Technology, Tunis, Tunisia, pp. 273-278.

[019] Yarmolik, S. (2008). Address sequences and backgrounds with different Hamming distances for multiple run March tests, International Journal of Applied Mathematics and Computer Science 18(3): 329-339, DOI: 10.2478/v10006-0080030-y. | Zbl 1178.94268

[020] Yarmolik, S. V. and Mrozek, I. (2007). Multi background memory testing, MIXDES07: Proceedings of the 14th International Conference on Mixed Design of Integrated Circuits and Systems, Ciechocinek, Poland, pp. 511-516.

[021] Zhang, B. and Srihari, S. (2003). Binary vector dissimilarity measures for handwriting identification, Proceedings of the SPIE, Document Recognition and Retrieval X, Santa Clara, CA, USA, pp. 155-166.

[022] Zorian, Y. (2002). Embedded memory test and repair: Infrastructure IP for SOC yield, ITC '02: Proceedings of the 2002 IEEE International Test Conference, Washington, DC, USA, p. 340.